DS-LFSR: a BIST TPG for low switching activity
نویسندگان
چکیده
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DSLFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is 1 th that of the normal clock, which drives the normal-speed LFSR. The use of DS-LFSR reduces the frequency of transitions at the circuit inputs driven by the slow LFSR, leading to a reduction in switching activity during test application. A procedure is presented to design a DS-LFSR so as to achieve high fault coverage by ensuring that patterns generated by it are unique and uniformly distributed. A new gain function and a method to compute its value for each circuit input are proposed to select inputs to be driven by the slow LFSR. Also, a procedure to increase the number of inputs driven by the slow LFSR by combining compatible inputs is presented to further decrease the switching activity. Finally, DS-LFSRs are designed for the ISCAS85 and ISCAS89 benchmark circuits and shown to provide a 13% to 70% reduction in the numbers of load-capacitance weighted transitions with no loss of fault coverage (for stuck-at as well as transition delay faults) and at very slight area overheads.
منابع مشابه
Review of LP - TPG Using LP - LFSR for Switching Activities
Test pattern generator (TPG) is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption, switching time and power dissipation without affecting the fault coverage. Low power linear feedback shift register (LPLFSR) is employed for TPG in order to reduce switching activities. This paper presents multiplier,...
متن کاملA Modernistic Approach to Design Fault Tolerant Circuit Using LP-LFSR with Low Power Dissipation
The aim of testing of VLSI circuits is high-quality screening of the circuits by targeting performance related faults. A low hardware overhead test pattern generator (TPG) for scan based BIST that can detect the any faults in the circuit under test and analyze their response .It is a new fault coverage test pattern generator using a liner feedback shift register (LFSR) called FC-LFSR can perfor...
متن کاملA New Approach to Design TPG for Low Power Testing Applications
VLSI circuit’s encounters are rapidly many challenging tasks of semiconductor manufacturing along operating with gigahertz range of frequencies. These challenges are include keeping peak power dissipation and the application time within limits. In this Paper we are proposes a new approach of low power Test Pattern Generator (TPG) designed by modifying parallel Linear Feedback Shift Register (Pa...
متن کاملA Modified Clock Scheme for a Low Power BIST Test Pattern Generator
In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roug...
متن کاملSwitching Activity Reduction Using Scan Shift Operation
This paper presents BIST TPG (built in self test) for low power dissipation and high fault coverage a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG subside transitions...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEEE Trans. on CAD of Integrated Circuits and Systems
دوره 21 شماره
صفحات -
تاریخ انتشار 2002